The present invention relates to the field of integrated circuits, and more specifically, to improving the interfacing of integrated circuit in a mixed-voltage environment.
The integrated circuit business and semiconductor industry are continually driven to reduce cost, reduce power, and improve performance. The integrated circuit products include microprocessors, memories, programmable logic, programmable controllers, application specific integrated circuits, and many other types of integrated circuits. Price reduction is strongly driven by migrating products to scaled processes, which reduce die sizes and increase yields. Power reduction has been achieved by circuit design techniques, power management schemes, and parasitic scaling, among other factors. Performance improvement has resulted from design techniques, process enhancements, and parasitic scaling, among other factors.
Process technology is improving. Resulting from the continual scaling and shrinking of device geometries, device sizes and dimensions require the operating voltages to be scaled. Operating voltages have been scaled down from 5 volts to 3.3 volts. This has resulted in the need for mixed-voltage-mode systems. That is, integrated circuits will need to interface with various operating voltages. And, further reductions are expected in the future. This industry provides products and printed circuit boards (PCBs) that utilize both 3.3-volt and 5-volt integrated circuits and devices. It is expected that there may be a considerable transition period for the standard power supply to switch from one voltage level to a lower voltage level.
Process scaling is the dominant method of reducing the die cost. The cost is achieved by receiving higher yields associated with smaller die sizes. Presently, power supply voltages are being reduced as the scaling progresses towards device dimensions that necessitate the reduction of voltage differences across these dimensions.
All manufacturers have not switched over to the lower power supply, simultaneously. Thus the scaling of the operating voltage has resulted in creating a multiple voltage mode industry. Integrated circuit companies must provide products capable of addressing the needs during this intermediate phase before the industry transitions to a single lower power supply voltage. It is expected that this industry will require some time to successfully transition over to the lower power supply.
As can be seen, an improved technique of fabricating, and operating integrated circuits is needed to meet these demands. These integrated circuits should interact with devices that are designed to operate at either the standard or the new lower power supply. The integrated circuit should also provide a cost reduction path to customers that continue to design 5-volt-only systems. Integrated circuits should provide the manufacturer with the flexibility to chose the market to support with a minimum cost and the shortest time to market.
The present invention is a technique of interfacing an integrated circuit in a mixed-voltage mode environment. In particular, an input/output driver or buffer of the present invention may interface directly with a voltage at a pad which is above the supply voltage for the input/output driver. This may be referred to as an xe2x80x9covervoltage condition.xe2x80x9d For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver of the present invention will tolerate this voltage level and prevent leakage current paths when used as an input. The present invention may also be used in a scheme where there is separated noisy and quiet supplies. For example, there may be a noisy power supply and quiet power supply. An I/O driver may be coupled to the noisy supply, and the core would be coupled to the quiet supply. This provides some isolation of noise at the I/O driver from coupling to internal circuitry. In an embodiment, a well-bias generator and level corrector are included in the output driver circuitry to prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit.
More specifically, the present invention is a high-voltage-tolerant interface circuit for an integrated circuit includes a first pull-up device coupled between a first supply voltage and an I/O pad. A second pull-up device is coupled between a second supply voltage and a first control electrode of the first pull-up device. And a third pull-up device is. coupled between the second supply voltage and a second control electrode of the second pull-up device. A third control electrode of the third pull-up device is coupled to the first control electrode, and a body electrode of the second pull-up device is coupled to a body electrode of the third pull-up device.